I wish to set up a PCG to drive the sample clocking an ADC and for the IDP PDAP unit which is connected to the ADC reading data into the SHARC. The PDAP will run in byte packing mode. The PCG will drive the PDAP @ 20MHz to read a 16:8 muxed ADC bus sampling at 10Mhz. The 10 and 20Mhz clock are generated from the same PCG so I can guarantee phasing. The mux select is fed by the same sample clock for the upper/lower byte selection (clock low = d0-d7, clock high = d8-d15).
The issue is that I need to synchronize the PDAP packing with the upper/lower byte selection so my data is always framed properly. But there doesn't seem to be a nice way to do this:
- The PDAP only has a frame sync output (PDAP Strobe), and no option for frame sync input
- The PCG does not have a frame sync input to externally control or reset the phasing on the clock generation
I see two options:
- Take the PDAP Strobe externally to the reset on a 1-bit flip-flop that counts sample clocks and whose output drive the data mux select. The issue with this is I need an external pin (which I don't have), and the external register creates issues as far a propagation delays in the whole sampling chain.
- Carefully control the start the PCG and PDAP and hope and pray the packing unit and PCG maintains sync for extended acquisitions sequences. This isn't unreasonable since the PCG will be the clock source for the PDAP, however this still makes me nervous that there is no hardware framing going on and any software timing glitch could get these two units out of frame sync.