I am using AD9910 on a PCB (not the evaluation board). I am now feeding a 15 MHz sine signal (Vpp~1V) into a balun on the PCB, then it is feed into the reference clock (REF_CLK) pins(pin 90 & 91) of the chip. The Vpp across the 2 reference clock is about 200mV. However, the output of the SYNC_CLK is not at 15/4 MHZ. Rather it is a 30MHz signal of 1 Vpp.
After the chip is reset, i.e. MASTER_RESET reaches logic high, the PLL multiplier is disabled.
I have populated the PLL components. Their values are
R 90 ohm C1 820pF C2 27 pF.
But I am uncertain how can the chip enable the PLL multiplier after it has been reset.
1)How can I control the register of the chip when the system clock is not yet set up? In other words, can I use a lower than 60MHz clock source to program the DDS chip?
2) If I have a reference clock signal of 26MHz, can I enable PLL multiplier (by changing register bits) and multiply it to 800-1000MHz? If yes, how can I use only this source with a microprocessor to program the DDS chip?
3)If I first reset the chip by a logic high on MASTER_RESET. Then feed in a 100MHz sine signal (1 Vpp). How can know the chip has set up a system clock? Must I look at SYNC_CLK and see if it is 100/4=25MHz or is there another way?