For cycle-accurate synchronization of two AD9122s, we plan to use "data rate mode." We'll provide a non-repeating FRAME pulse and the DCI clock at the data sample rate from an FPGA and REFCLK (aka SYNC) from a low jitter clock source. The same low jitter source also provides the clock to the FPGA so frequency and phase are locked throughout the system
Do we also need to drive the DACCLK inputs, or can the clock multiplier on the REFCLK input generate the DACCLK signal internally?
And if we do need to drive both of the inputs, can DACCLK and REFCLK be the same frequency?