I'm still using the AD9705 within my current research project and I'm wondering if the converter has a latency of one clock cycle. Within my measurements I notice the fact that DAC data transitions on the falling edge of DAC clk but the DAC output changes not on the next rising edge but on the one after that.
I'm driving the DAC with a single ended clock (CLK+ is driven , CLK- is left floating) with 30MHz. But I've also tried (for test purpose) to use a clk-frequency of only 300kHz and the behaviour is still the same.
The optional deskew-mode is disabled which I ensured by reading the register at adress 0x02. If I turn the deskew mode on, there is an overall latency of two clock cycles.
Does anyone have an idea what this behaviour comes from? Does the DAC have an inherent pipeline latency or anything like this?