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adv7180 can't maintain vertical sync

Question asked by pcrist621 on Mar 26, 2013
Latest reply on Apr 10, 2013 by pcrist621

I have a situation where a customer is trying to decode an analog video signal from a prototype IR camera using an adv7180 video decoder and is having difficulting maintaining vertical sync.




The camera generates a video signal using an ADV7393 video encoder running at 27MHz. The video encoder is driven by an FPGA using 8-bit 4:2:2 YCrCb Mode and the BT.656 standard. Because we are displaying a custom array of 320x240, some modifications were made to the tradtional digital stream designed for an NTSC active resolution of 720x486 for 525/60 video systems.

  • For the horizontal resolution, we are adding “black bars” (40 on each side) to the upsampled 640 pixel row data stream.
  • For vertical resolution, we are adjusting the vertical blanking intervals for 480 lines of active video.

                     Lines 1-22            22 lines of vertical blanking

                     Lines 23-262       240 lines of active video (odd field)

                     Lines 263-285       23 lines of vertical blanking

                     Lines 286-525     240 lines of active video (even field)

                                              525 total lines

Note: This is similar to the blanking intervals for square pixel mode as outlined in the Intersol App Note AN9728.2.


The initial configuration script used for the ADV7393 at power  up is outlined in table 65 on page 93 of the ADV7393 data sheet.

Subaddress      Setting                      Description    

     0x17                  0x02                       Software reset

     0x00                  0x10                       Only DAC 1 enabled, PLL enabled (16x) (Note: we are using the WLCSP package)

     0x01                  0x00                       SD input mode

     0x80                  0x10                       NTSC standard. SSAF luma filter enabled. 1.3MHz chroma filter enabled.

     0x82                  0xCB                      Pixel data valid. CVBS(composite)/Y-C (S-video) out. SSAF PRPB filter enabled.

                                                                Active video edge control enabled. Pedestal enabled.


All other registers are left in their post reset status.


This design is displaying video on several different LCD display monitors without issue. We can also use the analog video signal to properly capture videos using Star Tech's USB2.0 video capture cable.



  1. Would the alteration of the vertical blanking intervals discussed above be sufficient to prevent the ADV7180 from maintaining vertical sync?
  2. If not, are there any register settings on either the ADV7180 or the ADV7393 which can solve this problem?


I've attached a pdf file from our customer outlining the problem with pictures and osciloloscope screen shots.