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ADXL362 STATUS Clear Latency

Question asked by inagai Employee on Mar 26, 2013
Latest reply on Apr 26, 2013 by inagai



In order to check how long we need to wait to clear STATUS register after reading it, I took scopeshot as attached.

CH1 (Yellow) is INT1, on which Activity interrupt is assigned, and CH2 (Blue) and CH3 (Purple) are SPI-CLK and SPI-MOSI respectively.

As you can see, INT1 cleared about 30us after finish reading STATUS and CLK stops.

I could not find any latency description other than data ready on the datasheet, but is this 30us of latency looks reasonable and consistent with design?