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Memory architecture of ADSP-BF609

Question asked by Jayapriya on Mar 26, 2013
Latest reply on Mar 28, 2013 by Jayapriya

ADSP-BF609 is a dual core processor.
My questions are :

1.How do we diffrentiate between core 0 & core 1 ?? Is it divided linearly like core 0
first and then core 1 ??

As per Memory map from datasheet ADSP-BF69 ,
Core 0 = L1 instruction SRAM(64KB) = 0xFFA0 0000
Core 0 = L1 instruction SRAM(64KB) = 0xFF61 0000
So is it been differentiated w.r.t address ??


2.Where do we flash the code ??Flash is not mentioned clearly(Which address)


3. "Async Memory Banks" and "DDR2 or LPDDR Memory" are relevant only if
we use external memory ??