I am designing a board using ADSP-BF526 (400Mhz).
For the same I used the reference of the ADSP eval board as mentioned on the site.
For Booting the memories provided are M58WR032KB, NAND02G, MT48H32M16 and SST25WF040.
Mentioned below is the table of Vih Vil Vol Voh I have created for the verification of the design
|FPGA, PORT 0,1||3.3||0.8||2||0.4||2.9|
|FPGA, PORT 2,3||1.8||0.38||0.8||0.45||1.35|
Please notice there are violation in the following
- 1. ADSP Vol and Vil of MT48H32M16
- 2. ADSP Voh and Vih of MT48H32M16, M58WR032KB, NAND02G
As these are the same parts that are being used in the eval board, please clarify on the above mentioned violations. Or please sugest an alternate way of getting around the Violation
Also along with the ADSP I am interfacing a Spartan FPGA which will on the EBIU bus. Here to I have a violation of Vil(fpga) and Vol(adsp). Please can you help with the same.