I have small confusion on the selection of Multiplier Select in Clock Generation Unit(CGU) module.
The range of MSEL is from 1 to 127.
1) In Revision 0.41, June - 2012(document is attached):
The valid range of CGU_CTL. MSEL settings is from 8 to 50 in decimal. All other settings are reserved. (Page No: 3-10)
2) Latest release Revision0.5, Feb -2013( http://www.analog.com/static/imported-files/processor_manuals/blackfin_hwr_bf60x_rev0.5.pdf )
Ranges are not mentioned in document. In register it is mentioned as See the product specific section of the CGU for additional notes. But I didn't find the proper value of it. Can you please help me out.
These registers(CGU_CTL.MSEL) must be set such that the minimum and maximum clock specified in the data sheet are not violated. All other clock specifications in the data sheet must also be adhered to for correct operation of the part.
Below are considered values to calculate PLLCLK frequency.
Formula: PLLCLK frequency = (SYS_CLKIN frequency / (DF+1)) * MSEL
SYS_CLKIN frequency = 25MHz
DF = 0
MSEL = 21
Output of PLLCLK frequency is 525MHz. As each core clock supports up to 500 MHz. In that case the output of PLLCLK frequency is valid?
Thank you in advance.