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The serious problems with AD9970

Question asked by davidzhang on Mar 23, 2013
Latest reply on Mar 25, 2013 by davidzhang

I have modified my register settings ( in reverse order) as Analog Device reference design as below:

x"004D0004000", -- enable sync 65

           x"004A000ffff", -- 7th sync

           x"00490000000", -- 6th sync

           x"0048000ffff", -- 5th sync

           x"00470000000", -- 4th sync

           x"0046000ffff", -- 3rd sync 60

           x"00450000000", -- 2nd sync

           x"0044000ffff", -- 53 1th sync

           x"00430000007", -- sync words number 7 from 52 to 58 -- 20

           x"00410000259", -- LVDS clock delay 62 before

           x"00400000000", -- 55

           x"003700041a6", -- 50 Dout phase control

           x"00360010840", -- SHP SHD smapling SHP50 SHD28

           x"00350555555",

           x"00340000000",

           x"00330011000", -- reset 50

           x"00320002808", -- HL

           x"00310012606", -- 44 H2

           x"00300012606", -- H1

           x"00230000024", -- Mode 1

           x"00210000001", -- 45

           x"00110000001", --

           x"00140000001", -- need 100us writing time  43

           x"000600001Ec", -- 5

           x"0005000000f", -- VGA gain

           x"00040000001", -- CDS gain 40

           x"00010000008",

           x"00000000000", -- need 500us writing time  38

           x"002C0000000",

           x"002B0000000", --

           x"002A0000001", -- 35

           x"081F0001fff", --

           x"081E0001fff",

           x"081D0001fff",

           x"081C0000001", -- PBLK toggle polarity

           x"081B0001fff", -- 30

           x"081A0001fff",

           x"08190001fff",

           x"08180000001", -- CLPOB toggle polarity

           x"08170000000", 

           x"08160000000", -- 25

           x"08150000000", --

           x"08140000800",

           x"08131000800",

           x"08121000800",

           x"08111000800", -- 20

           x"08101000000", 

           x"080F3ffffff",

           x"080E00ee00f", -- PBLK  toggle position

           x"080D3ffffff",

           x"080C0a92637", -- CLPOB toggle position -- 15

           x"080B0000000", -- for test only

           x"080A0000000", -- HBLK end position

             x"08090400000", -- HBLK mask for H1,H2, H3, H4 and HL. H2and H4 high

           x"08080000000", -- HBLK length in mode 1 and mode 2

           x"08070000000", -- 10

           x"08060000000", -- HBLK start position --35

           x"08053ffffff",

           x"08043ffffff",

           x"080300ee00f", -- HBLKOeven line

           x"08023ffffff", -- 5

           x"08013ffffff",

           x"080000ee00f", -- HBLKOdd   line

           x"00280000001",

           x"00100000001"

 

The 160MHZ clock from ADC was fed into FPGA PLL but this clock lost lock as shown in attached image:

 

PLL unlock.png

 

You also can see there is wired signal on LVDS data signal line as shown attached image.

nnd 004.JPG

 

 

I got the CCD analog signals as below but I cannot get digital signals, it is so frustrated.

lld 001.JPG

 

Please help  ASAP.

 

Many thanks.

 

David.

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