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Data Transfert from FPGA to AD9779A

Question asked by e.gatti@electrosys.it on Mar 21, 2013
Latest reply on Mar 25, 2013 by Tguy

On Page 46 of AD9779A datasheet there is a paragraph "INPUT DATA REFERENCED TO DATACLK". In this paragraph there is showed the Figure 82. Is this Figure 82 valid also if I set 4x interpolator on the AD9779A ? In other words, if I use 4x interpolator, is it possible to referece the input data to DATACLK (pin 37)? For example I send the data at 115 Mb/s with the PLL dsabled. The REFCLOCK (pins 5, 6) is 460MHz, so I use the internal AD9779A 4x intepolator. In this case, is it possible do not use the Sync_I signal (pins 13, 14)? Is it possible to set the Sync_I signal on undefined mode ? In other words, is it possible do not connect the Sync_I pin 13 and 14 at any device? Enrico

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