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AD9779A automatic timing optimization

Question asked by takashi on Mar 19, 2013
Latest reply on Mar 26, 2013 by takashi

I'm using automatic timing optimization mode of AD9779A.


According to the datasheet, DATACLK Delay is increased if a setup error is detected.

In my test board, interrupt reg keeps showing setup error (data timing error IRQ=1 & data timing error type=1),

but dataclk delay remains at some value (0x0a etc.), not reaching maximum value of 0x1F.


When I change DATACLK frequency, delay value also changes. So automatic mode seems working.

Interrupt register is not updated in auto-mode? If so, how can I know if timing error is avoided?


One more question, I'm using timing margin value = 0x01. What is the unit of timing margin and recommended value?