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LVDS clock Buffer - output swing (AC coupling)

Question asked by veera on Mar 14, 2013
Latest reply on Mar 15, 2013 by Kyle.Slightom


We are providing LVDS clock to DACs (AD9781) through the clock buffer. We are AC coupling the clock signal.

While we perform simulation on various LVDS buffers (using IBIS models), we are seeing that some AC coupled differential signal (when measured through differential probe) are swinging from 0 to +2Vswing, while signals from some other devices are swinging from -Vswing to +Vswing with 0 as center. While using Differential probe, one signal is centered around 0V while other is centered around Vswing.

I am attaching images of both the signals. I would like to why is this difference seen among LVDS buffers. Is it because difference in CMOS and Bipolar architecture?

Can DACs and ADCs accept both these kind of clocks (even both clocks have same common mode voltage)