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Blackfin Interrupt Latency

Question asked by yanming on Mar 13, 2013
Latest reply on Mar 26, 2013 by SachinV

Hi! All,

 

     I have a question when porting a kernel to Blackfin processor. Suppose I have the following code:

 

                         cli R5;     //disable all interrupts

                         Enable Interrupt 14;

                         R0 = 0;

                         raise 14;

                         R0 = 1;

                         R0 = 2;

                         R0 = 3;

                         ... ...

    

       Is it safe to say when interrupt 14 occurs, at least R0 gets value of 1? If I change the above code to the following:

                        

                         cli R5;     //disable all interrupts 

                         Enable Interrupt 14;

                         R0 = 0;

                         raise 14;

                         RTS;

                         R0 = 1;

                         R0 = 2;

 

     When interrupt 14 occurs, can I assume that the instruction pointed to by RETS already begin executing?

 

      Thanks in advance!

 

Yanming

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