We are deriving clock for AD9781 from a LVPECL clock Buffer.
The clock signal to CLKp and CLKn pins are shown in the attached figure (black & blue - CLKp &Clkn ; Red - Differential value). We can see the common mode voltage of 0.4 as required. However as you can see, the differential clock is not swinging from -600mV to +600mV (like LVDS line), but instead swinging from 0 to 1200mV. We derived these figures through SI analysis. Is this clock acceptable or should the differential clock be centered to 0V like normal LVDS?