We are deriving clock for ADC from a LVDS clock Buffer.
The clock signal to CLKp and CLKn pins are shown in the attached figure (blue & red - CLKp &Clkn ; Green - Differential value). We can see the common mode voltage of 0.9 as required. However as you can see, the differential clock is not swinging from -400mV to +400mV (like LVDS line), but instead swinging from 0 to 800mV. We derived these figures through SI analysis. Is this clock acceptable or should the differential clock be centered to 0V like normal LVDS?