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ADF4158 Muxout Serial Data out shifted 1-bit left

Question asked by StephaneRey on Mar 13, 2013
Latest reply on Mar 14, 2013 by StephaneRey

Hi there,


I've designed a board using an ADF4158 fractional PLL. The PLL is working fine.


My PLL has a 850-1050 MHz VCO attached and an active inverting loop filter with values coming from ADISimPLL

I'm trying to get the simplest configuration for the moment just to ensure that it works

I'm sending R0, R2, R1 and R0

The first R0 sent is in order to set MUXOUT to SERIAL OUT in order to check what the PLL receives.


R0 = 0x38 0x2D 0x00 0x00 (FRAC_MSB = 0, INT = 90, MUXOUT = SERIAL_DATA_OUT, Ramp=Disabled)

R2 = 0x0F 0x00 0x80 0x02 (ClockDivider =0, R_counter = 1, Ref_doubler = 0, R_divider = 0, prescaler = 4/5, CP = 5mA, CSR_EN = 0)

R1 = 0x00 0x00 0x00 0x01 (FRAC_LSB = 0)

R0 = 0x38 0x2D 0x00 0x00 (FRAC_MSB = 0, INT = 90, MUXOUT = SERIAL_DATA_OUT, Ramp=Disabled)


My SPI is made by software. The attached picture is a screenshot of the logic analyzer. Bus #1 is the data I sent, Bus #2 is the MUXOUT serial data out with same clock and LE signals (just a copy on the analyzer screen)




It appears that the first 32-bits data coming out from MUXOUT is the last data sent the last time (last R0), shifted left by 1-bit. Then the 2nd 32-bits value is the copy of the first transmitted in that screenshot (first R0) again shifted left by 1-bit.

I guess this is not normal this shift left. But the datasheet is not detailled enough to understand the in and outs of this serial out


The only difference I see between the ADF4158 writing timings and my screenshot (see pictures attached) is that in the datasheet LE is raised at the end of a 32-bits data during the last clock high level whereas with a SPI it can only be done after the clock fall down again but I don't think this might be the issue as the PLL is very likely gating on the rising edges.


Any clue or advise on how to investigate further ? I'm stuck ....