My question is concerning the Signal Integrity for the ADV7513. I am trying to come up with a noise margin for this chip to design my power system properly, but the results do not make much sense. The voltage drop inside the pakage is too high....Please correct me if I am wrong in my analysis.
The voltage drop inside the package can be calculate using (VL=L.Di/dt)
-Assuming edge rate on data pins 1ns (it can be smaller based on the IBIS): dt
-Assuming that we set the drive strength control to 24 mA (estimation from IBIS model): di
-Assuming the package inductance of 6nH (from IBIS model): L
Now assuming that each DVDD_IO pin supplies power for 8 pins on the output....it is easy to see that we can have a voltage drop of 144mV per pin so say five pins switch at the same time the noise will be greater than 0.5V. Which is at the very least questionable. Can anyone help me out with this?
ANY HELP IS MORE THAN WELCOME!!
THANK YOU VERY MUCH