Design requirement: Set the AD9122 TxDAC to output a baseband I&Q signal centered at 320M with 83M BWidth (320+/-42.5MHz) into an ADL5375 IQ MOD. The LVDS data input rate is 256Msps, alternate I&Q, equivalent to 128M complex data rate ( I+j*Q), centered at 0Hz (baseband).
In my case, Fout/Fdata =320/128 = 2.5. Per Fig 59 of AD9122 data sheet for x8 interp, the BWidth for frac(Fout/Fdata) =0.5 is 0.5*Fdata =64M <83M. Is this correct, that I cannot achive 83M BWidth with the center shifted to 320 MHz?
I set the AD9122 as follows:
Coarse Mod: Fs/4; shifts Center by 256M
NCO Freq =256Mn = (2*Fdata);
NCO Freq Shift =64M
Total shift =320M,
The interpolation factor is 8, so the DAC clock is 8*128= 1024MHz. For DAC o/put freq range =(320+/42.5M), the LPF on IQMOD baseband inputs was designed to pass 380M, and rejects aliases from 670M and up. I test with two simulataneous tones varying in frequency between between -43 and +43MHz; the IQMOD LO is 2.18G, and the spec analyzer is centered at 2.5GHz. Worst case spur is 2.29G; well outside a passband of a filter of 100M wide BPF centered at 2.5G. So , I think I can achieve my design goal.
Can you expalin what the "ENABLE ADVANCED FILTER CONTROL" section of the AD9122 SPI COntrol GUI does? What is the difference between DC and Shifted DC in the Coarse Mod control -same question for "Fs/4" and "Shifted Fs/4"? and the remaining variants?