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How to do VHDL coding for stream cipher's PSEUDO-RANDOM sequence?

Question asked by manasi13042 on Mar 9, 2013
Latest reply on Mar 11, 2013 by DaveD

Hello, i hav ISE9.1

I want to generate a sequence in which input is XORed with the key"k"and then rotated. After that last two LSBs are XORed and put at MSB other three shifted to right and given back to input(feedback). I executing the program. I'm not getting the output..

 

entity counter is

 

port (clk,en:in std_logic;

       p: buffer std_logic_vector (3 downto 0):="0011";

       c: buffer std_logic_vector (3 downto 0);

       k: in std_logic_vector (3 downto 0):="1100");

end counter;

 

 

architecture behav of counter is

   begin

      P1:process(clk)

         begin

           if (clk'event and clk='1')then

             if en='1' then

                for i in 0 to 3 loop

                    c(i)<=p(i);

                end loop;

             else

                for i in 0 to 3 loop

                    c(i)<= p(i) xor k(i);

                end loop;

             end if;

            end if;

    end process P1;

 

 

       P2:process (c)

          begin

            c=(c(0)) & (c(3 downto 1));

          end process P2;

 

 

    for i in 0 to 3 loop

        p(i)<=c(i);

    end loop;

 

end behav;

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