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AD9789 clocking

Question asked by Jaime on Mar 6, 2013
Latest reply on Mar 11, 2013 by danf
Branched from an earlier discussion

Hello, I would thank you very much to reply this also about AD9789 clocking. We plan to use the AD9789 for a broadcast application. We plan to use a very low jitter device as clock with multiple outputs, specified less than 130fs total jitter 100Hz to 20MHz. We think this device is superior to AD9518-2 that we planned before. But both of them cannot deliver 1.4Vpp to the DAC that is an AD9789 minimum specification. That is why you recommend use ADCLK914 comparator. But if we use it as recommended we add 100fs more, and I wonder if this will enworse the signal quality in terms of MER/EVM (our 32k OFDM/256QAM signal is very sensitive to clock phase noise). Normally most of the clock jitter is 1/f, while I guess the comparator jitter distribution is different. There are devices comparator-type in the market that can add only 17fs jitter (100Hz to 100 MHz), but they can't deliver 1.4Vpp but a standard LVPECL signal or a maximum of 0.8Vpp at this frequency (on 100ohm); slew rate is still about 0.5V/90ps at that frequency (5.5V/ns). Moreover the recomended differential termination at the DAC clock input seems to be 50 ohm in AC, not 100 ohm as normally specified. I wonder if it is either preferable, or mandatory, to drive the AD9789 with 1.4Vpp using ADCLK914 but adding its 110fs additive jitter, or do it with a slightly smaller amplitude signal but with better jitter and similar slew rate. Is the 1.4Vpp an absolute requirement or it is calculated based on a sinusoidal signal slew rate, for instance? (because for a 1.4Vpp sinewave slew rate is not faster, about 1.26V/250ps=5.04V/ns)

 

Thanks in advance

 

Jaime Martin

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