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ADAS1000 meaning of 'Configuration status' bit of OPSTAT register?

Question asked by jdesbonnet on Mar 5, 2013
Latest reply on Feb 1, 2016 by CatherineR

I'm in the process of writing a software driver for an ADAS1000 ECG front end. Right now I'm just focusing on basic SPI IO, so my hardware setup hasn't got any of the analog inputs connected yet. I can read/write registers ok. I can also read data frames (I'm expecting only a little noise as there is nothing connected right now), but it's all zeros across the board. I would have expected a little noise from a functioning ADC. I notice the frame header has value 0xc00000 ('ready bit' set to busy) and the OPSTAT register reads 0x04 (Configuration status set to busy).


The explanation of the OPSTAT configuration status is rather vague: "[if bit set] the configuration has not been read yet. Once the configuration is set, this bit is ready [ie cleared to 0]."


Can anyone clarify what might cause OPSTAT configuration status to be set to busy? I'm reading OPSTAT after setting CMREFCTL, FRMCTL, ECGCTL: so the device should be configured.