We have a custom BF537 based board with a NAND flash connected to the data bus & using GPIOs for commands and ready status. We're running rev. 3.0.8-ADI-2011R1-svn5 and using the plat-nand.c driver in linux/driver/mtd/nand. Our board resource file is based on the bf537 stamp.c file.
We were having extremely slow responses with the NAND due to timeouts on the ready status signal, which eventually caused the watchdog to time out. It appears that in the resource file, the function bfin_plat_nand_init() only declares the GPIO line used for ready status as an I/O line, but does not set the direction (set up the DIR register) nor enable the input buffer (INEN register). The attached patch (which makes a call to gpio_direction_input()) seems to fix this problem. A quick look at the buildroot release also indicates the problem exists in the latest release also.