Hello, what is the required duty cycle for the MCLK input to the AD7764?
I can't find a specification in the data-sheet.
With MCLK duty cycle of 30/70, the AD7764 can still work properly. It is fine setting the MCLK this way and will not degrade its performance.
We're looking into this. We'll provide our response soon.
Can we ask at to what extent you want to push the MCLK duty cycle? Normally, it should be maintained at its 50% duty cycle. However, the AD7764 can deal with a wide range of duty cycles. The MCLK gets divided internally with a divider and it is the internal clock that is used for sampling the analog input. The divider cleans up any duty cycle irregularities, thus making AD7764 immune to MCLK duty cycle.
Hi Johnny, thanks for the response. The duty cycle we wanted to use was 30/70.
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