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SPIx_SEL1 Output Pulses

Question asked by spflanze on Feb 28, 2013
Latest reply on Mar 27, 2013 by Prashant

When the SPI interface is used to send data using chained buffers, and where there are two buffers in the chain, will the SPIx_SEL1 output be pulsed high after first buffer is transmitted and before the second buffer is?


The processor is a BF547 and the operating system is VDK.