I'm attempting to migrate a piece of software ( zedboard, no-os) that utilizes the AD9467-FMC card for analog to digital conversion. The software predates the release of the AD9517 driver. No external clock source exists so the card has been reconfigured to use the optional oscillator. Using the the code included in the reference design for the FMC card a zero error delay can be found after a running adc_setup a few times. Using the chipscope plot it can be verified that the AD9467 AD-converter is now clocked by a 250 MHz clock.
So far, so good.
My problem is that I need the option to set a lower frequency. If I recall the datasheet for AD9517 correctly the clock signal can be routed through the VCO divider and/or the output channel divider, both programmable to some extent. For my purpose division by 2 or 4 would be suitable (resulting AD sample rate 125 MHz or 62,5), which would seem easy to accomplish. But short of internalizing the code for the driver It's not clear to me how to accomplish this. Is there some documentation available, or in the pipeline, describing the driver in some more detail? Should I be able to accomplish this using the driver functions (other than writing to registers manually)?
It would seem like the ad9517_frequency function is something like I want, but naively attempting to set a lower value here has no effect.