I'm currently implementing an ADSP-21369 and I was thinking about the booting scheme. I have a SPI Flash ROM connected to a FPGA (SPI host) and this FPGA is connected to the SHARC DSP. I'd like to use the SPI master booting mode (DSP is master). To sum-up SPI Flash PROM will be remotly programmed via the FPGA. When a boot will happen, FPGA will read the SPI flash and send the boot data to DSP. My question is so:
- When a power-up occurs the FPGA will boot and might not be ready before the DSP. Is the DSP will initiate the booting SPI communication after a power-up (electrical cycle) or after a reset coming from the FPGA?
Sorry if this question seems to be a bit trivial. But I'm a complete newbie in DSP's....
Thanks in advance for your reply.