AnsweredAssumed Answered

Cannot access SDRAM properly

Question asked by Naik on Feb 22, 2013
Latest reply on Feb 22, 2013 by Andreas

Hello,

 

I am using ADSP-BF533 EZ Kit lite board, revision 2.2 with VisualDSP++ 5.0 and HPUSB-ICE Emulator.

I am trying to run SDRAM test using the example code "Power On Self Test" provided in VisualDSP.

 

I have modified the project to run SDRAM test only.

The test runs successfully with "0x00000000" as the SDRAM Start Address and "0x4000000" ( 64Mb) as the SDRAM Size.

But when I change the SDRAM start address to anything other than 0x00000000 and size less than 64Mb, it throws an unknown exception with EXCAUSE value 0x24 in the sequencer status.

 

Below is the part of SDRAM Test:

 

////////////////////////////////////////////////////////////////////////////
//
//  Program to check the functionality of core accesses to SDRAM
//    device
//
//
// Purpose:  Perform a POST SDRAM on the BF533 EZ-Kit Lite
//
//
// NOTE: This test is used for BF533 EZ-Kit Lite rev 1.7 and above with 
//   MT48LC32M16 32M x 16 bits (64 MB) SDRAM on board
//
////////////////////////////////////////////////////////////////////////////
#include <cdefBF533.h>
#include <ccblkfn.h>

//////////////////////////////////////////////////////////////////////////////
//
// COMMON DEFINES
//
//////////////////////////////////////////////////////////////////////////////
#define SDRAM_START  0x00000003 // start address of SDRAM
#define SDRAM_SIZE  0x10//0x04000000 // size of SDRAM in bytes, MT48LC32M16 32M x 16 bits (64 MB)

//////////////////////////////////////////////////////////////////////////////
//
// function prototypes
//
//////////////////////////////////////////////////////////////////////////////
void Init_SDRAM(void);
int TEST_SDRAM(void);

//--------------------------------------------------------------------------//
// Function: Init_SDRAM             //
//                   //
// Parameters: None              //
//                   //
// Return:  None              //
//                   //
// Description: This function configures the SDRAM controller
//--------------------------------------------------------------------------//
void Init_SDRAM(void)
{
 // Initalize EBIU control registers to enable all banks 
 *pEBIU_AMBCTL1 = 0xFFFFFF02;
 ssync();
 
 // -- not sure why there is a read here, possibly anomaly 05000157?
 //temp = *pEBIU_AMBCTL1;
 //temp++;
 
 *pEBIU_AMGCTL = 0x00FF;
 ssync();
 
 
 // Check if already enabled
 if( SDRS != ((*pEBIU_SDSTAT) & SDRS) )
 {
  return;
 }
 
 
 //SDRAM Refresh Rate Control Register
 *pEBIU_SDRRC = 0x01A0; 
 
 //SDRAM Memory Bank Control Register
 *pEBIU_SDBCTL = 0x0025; //1.7 64 MB
// *pEBIU_SDBCTL = 0x0013; //1.6 and below 32 MB
  
 //SDRAM Memory Global Control Register 
 *pEBIU_SDGCTL = 0x0091998d;//0x998D0491;
 ssync();
}
//////////////////////////////////////////////////////////////////////////////
// int TEST_SDRAM(void)
// 
// PURPOSE:  Test the SDRAM
//////////////////////////////////////////////////////////////////////////////
int TEST_SDRAM(void)
{ 
 volatile unsigned int *pDst;
 int nIndex = 0;
 int bPass = 1;  // returning 1 indicates a pass, anything else is a fail
 
 Init_SDRAM(); 
 // write incrementing values to each SRAM location
 for(nIndex = 0, pDst = (unsigned int *)SDRAM_START; pDst < (unsigned int *)(SDRAM_START + SDRAM_SIZE); pDst++, nIndex++ )
 {
  *pDst = nIndex;
  ssync();
 }
 
 // verify incrementing values
 for(nIndex = 0, pDst = (unsigned int *)SDRAM_START; pDst < (unsigned int *)(SDRAM_START + SDRAM_SIZE); pDst++, nIndex++ )
 {
  if( nIndex != *pDst )
  {
   bPass = 0;
   return false;
  }
 }
 
 // write all FFFF's 
 for(nIndex = 0xFFFFFFFF, pDst = (unsigned int *)SDRAM_START; pDst < (unsigned int *)(SDRAM_START + SDRAM_SIZE); pDst++ )
 {
  *pDst = nIndex;
 }
 
 // verify all FFFF's 
 for(nIndex = 0xFFFFFFFF, pDst = (unsigned int *)SDRAM_START; pDst < (unsigned int *)(SDRAM_START + SDRAM_SIZE); pDst++ )
 {
  if( nIndex != *pDst )
  {
   bPass = 0;
   return false;
  }
 }
 
 // write all AAAAAA's 
 for(nIndex = 0xAAAAAAAA, pDst = (unsigned int *)SDRAM_START; pDst < (unsigned int *)(SDRAM_START + SDRAM_SIZE); pDst++ )
 {
  *pDst = nIndex;
 }
 
 // verify all AAAAA's 
 for(nIndex = 0xAAAAAAAA, pDst = (unsigned int *)SDRAM_START; pDst < (unsigned int *)(SDRAM_START + SDRAM_SIZE); pDst++ )
 {
  if( nIndex != *pDst )
  {
   bPass = 0;
   return false;
  }
 }
  
 // write all 555555's 
 for(nIndex = 0x55555555, pDst = (unsigned int *)SDRAM_START; pDst < (unsigned int *)(SDRAM_START + SDRAM_SIZE); pDst++ )
 {
  *pDst = nIndex;
 }
 
 // verify all 55555's 
 for(nIndex = 0x55555555, pDst = (unsigned int *)SDRAM_START; pDst < (unsigned int *)(SDRAM_START + SDRAM_SIZE); pDst++ )
 {
  if( nIndex != *pDst )
  {
   bPass = 0;
   return false;
  }
 }
    
 return true;
}
//////////////////////////////////////////////////////////////////////////////
//
// stand alone test jig
//
//////////////////////////////////////////////////////////////////////////////
#ifdef _STANDALONE_ // use this to run standalone tests
int main(void)
{
 
 do{
  if( 0 == TEST_SDRAM() )
  {
   asm("emuexcpt;");
  }
  
 }while(1);
    
 
 
 return 0;
}
#endif //#ifdef _STANDALONE_

 

Also, I have attached the project files for reference.

Please help to resolve this problem.

 

Regards,

Pradnya

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