In my project, i use 64MB DDR memory, and configure as default. I found the DDR memory is split into two, one half for each core in app.ldf. Address from 0x4 to 0x01ffffff is allocate for core0, and address from 0x02000000 to 0x03ffffff is allocate for core1. L3 is a shared memory, so i have a question about DDR memory. Can core0 read and write DDR memory address between 0x02000000 to 0x03ffffff? and how to?