I'm having a very frustrating time debugging some lock issues on the ADF4350 EB2Z. I want to use this as a frequency synthesizer from ~300 MHz to 2Ghz, with 10Mhz channel spacing. I'm using the onboard reference clock (10Mhz), and loop filter (~20khz, at charge pump current 2.5mA).
I've been programming it in integer-N mode, with
* PFD = 10Mhz
* prescalar = 8/9
* divided output as needed
I've also tried using both divided and fundamental feedback from the VCO.
It locks nicely at certain frequencies, but at other frequencies (seemingly at random), the PLL refuses to lock. For example, see attached spectra at 500Mhz and 1GHz.
In debugging, I tried stepping over frequencies from 400Mhz, to 4.4Ghz -- see google spreadsheet: https://docs.google.com/spreadsheet/ccc?key=0AjQWBGQVwam3dGEwQ3QyM1lNYTQwV2lIM2RwcmpidGc&usp=sharing#gid=0. It looks like there are certain VCO fundamental frequencies it's unable to lock at, and those are mapping identically onto the divided down RF output frequencies as well. Eg, I'm unable to lock at 440Mhz (8x divider at output, N = 352), which maps back from being unable to lock to 3520Mhz VCO fundamental (N = 352, undivided).
Any hints/suggestions? I'm relatively new to all of this, and so it's possible I've overlooked something obvious.