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Question asked by DRS-des on Feb 19, 2013
Latest reply on Feb 22, 2013 by J.Harris

I am testing AD9268 ADC with have HSC-ADC-EVALCZ  - it has 65k on-board memorywith VisualAnalog ver I test only one channel of the dual AD9268-125, using all the 65k memory for best noise floor. However, the noise floor breaks up at certain input freq. It does not break up for FFT lengths <=32k.


Eg ADC Clock Rate =128M input =166M; FFT clean with fund @ 38M. Change input freq to 166.3M, the noise floor bounces up & down.


Drop FFT length to 32k, the noise floor is consistent , no matter the input test freq.