is this coupling Reactive Loads with and witout transformers to the DDS AD9954 DAC output correct?
First of all I'm asking for arrowed resistors (resistance,position) and capacitor C1.
What is the characteristic impedance (z0) of the filter and was it designed for equal input/output loads?
Assuming the filter is of the equally terminated variety with z0 = 50 ohms, then:
R22 = 50 ohms
Determining R21 and R74 is a little more complicated. Impedance matching to the filter input requires the parallel combination of R21 and R74 to be 50 ohms. That is;
R21 || R74 = 50 ohms
From the perspective of the DAC IOUT pin, the load is:
R21 || R74 || R22 = 25 ohms
Hence, the load at the DAC -IOUT pin (R19) should be 25 ohms, thus balancing the two DAC output pins.
Now we need to determine values of R74 and R21...
R74 must be chosen to meet the DAC voltage compliance specification. The datasheet indicates the output voltage compliance of the DAC is VDD +/- 0.5V. Because we are dealing with a resistive termination, it is not possible to exceed VDD. This further limits the DAC output voltage compliance range from VDD - 0.5V to VDD (that is 0.5 V peak-to-peak centered on VDD - 0.25 V). Therefore, we need to choose R74 so that the mid-scale DAC current causes the output voltage to be VDD - 0.25V. That is, with the DAC load resistor connected to VDD it must drop 0.25 V when the DAC is at mid-scale current. Assuming the DAC full scale current is set for 10 mA, then the mid-scale current is 5 mA. Therefore:
R74 = 0.25V/5mA = 50 ohms
Because R21 || R74 = 50 ohms, we have:
R21 = infinity
Hence, R21 is not needed at all in this particular case.
So now we have the DAC output properly DC biased. What about DAC voltage compliance with regard to AC?
The voltage swing on the IOUT pin is a function of the DAC full scale current and the load at the IOUT pin. We previously determined the load at the IOUT pin to be 25 ohms. Hence, the peak-to-peak voltage swing at the IOUT pin is:
DACcurrent x DACload = 10 mA x 25 ohms = 250 mV (or 125 mV peak)
This means the voltage on the IOUT pin ranges from VDD - 0.25 - 0.125 V to VDD - 0.25 + 0.125 V, or VDD - 0.375 V to VDD - 0.125 V, which is within the limits.
Hope this answers your questions.
There is an evaluation board schematic for AD9954, I think it's a good reference for this.
unfortunately, evaluation board include only transformer design and I'm not sure the single end design.
For the single ended configuration, the important concept is that the terminated impedances, that is seen by each IOUT, are identical, symmetrical. As long as the -IOUT, which was used in this case, is terminated by the impedance seen by out +IOUT, then there won't be a problem.
Super, thank you for clarifying.
Retrieving data ...