We recently built a custom board with the ADSP-21489, which was spun from a previous custom board with the ADSP-21369. We used the ADSP-21369 EZKit as our reference for the first board and referenced the ADSP-21489 EZKit to spin the board for the ADSP-21489.
We originally had the SDRAM (MT48LC32M16A2) on Bank 1 of the '369 and a Lattic CPLD on Bank 0. We wanted the potential future use of executing code from the SDRAM on the '489 so we swapped the Banks (Bank 0 = SDRAM, Bank 1 = CPLD). On the '369 we never had issues accessing the SDRAM or CPLD, but when we switched to the '489 we could only access the CPLD and are unable to read or write to the SDRAM
Utilizing the emulator to attempt read and write the SDRAM we probed on the board and noticed we are not getting an assertion of MS0 or SDDQM, but do have an appropriate clock signal (133MHz) coming from SDCLK. We have verified that we can read and write to the CPLD on Bank1 and probed the MS1 line and verified it was asserting. We have gone through and verified all the settings of the SDRAM controller on the '489, but have not seen a "smoking gun" as to why we can't read or write to SDRAM.
Another issue we ran into and believe related is we setup the SPORT after the SDRAM and send some initialization values to devices attached to the SPORT. After words we attempt to initialize a section of the SDRAM at which point we get an error from the emulator "Core Hang Detected on Device 0, Core access to SPORT/LINK Port is hung at PC:0x08fa29" we have never seen this error message before, but we believe it may be in relation to the SDRAM access problem.
We have reviewed the Silicon Anomaly List and are unsure if 15000020 PLL Programming issues is causing these problems or not. We have implemented the workarounds mentioned with no success.
Any insight or advice on this issue would be greatly appreciated.