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AD 9979

Question asked by dlamba on Feb 12, 2013
Latest reply on Feb 14, 2013 by TFAnalog

There are two apparrently conflicting elements in the AD 9979 timing specification. Namely, on Pg3 the minimum frequency of the CLI signal is said to be 8 MHz. On the very next page however, the clock period is said to have a minimum value (implying an upper limit on the frequency) and no maximum value, which suggests that there is no lower limit on the CLI frequency. In other words, the clock frequency can be driven as low as one wants.

I am trying to drive a Hamamatsu S01420 sensor, which can only output the pixels at a maximum of 500 kHz. The AD9979 datasheet suggests that the CLI frequency should be made equal to the pixel clock frequency, so I have a 500KHz clock connected to CLI.


I am writing SPI commands to the chip as suggested and using the example on Pg 36. In addition I am setting the necessary H1LOC and H2LOC registers.


However, we have been trying to get the AD9979 to generate H1-H4 for a while now, and cannot get it to work.


Am I missing something with an easy fix, or is the highlighted line above the fundamental problem.?