We're using the AD9613 is our system and we're planning on using an FPGA to interface to the LVDS output bus. The timing spec specifies DCO to Data Skew as Min = 0.4nS Typ = 0.7nS Max 1.0nS. With other devices I always seen skew spec'd as a plus/minus parameter (i.e. ±400pS) or given in terms of Tsu and Th with respect the the receiving device. The AD9613 data sheet lists skew as only being positive. Is that correct? Here's what I'm thinking...
- The interface will be running at 180MHz. I'll setup the PLL on the FPGA to shift the incoming DCO clock by 90°, plus 700pS, as that is the typical clock-to-output delay (from the Tskew parameter in the datasheet). This should center the clock that the FPGA will use to capture the data between data transitions... Theoretically giving the best setup/hold times.
- As far as input/output delay (which the FPGA fitter uses to make sure setup/hold times are met) I'll use a minimum and maximum of ±300pS (700pS - 400pS and 700pS - 1000pS).
Could you let me know if I'm on the right track?