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AD9552 etc. as clock cleaner

Question asked by RTF on Feb 6, 2013
Latest reply on Feb 11, 2013 by pkern

HI !

I need to perform 16bit AD end 14bit DA conversion. Sample rate are variable from 50 kHz to 1MHz with 10 kHz step.

FPGA or microcontroller (MCU) has a clock jitter which is not suitable for precision ADC&DAC.

I want to use  PLL based clock generator such as AD9552 and ADF4002 as divider.

As possible to use MCU master clock out pin as reference for AD9552?

I fear that the uC clock jitter will not yield the expected performance of AD9552

Is it possible to calculate the output jitter, assume the jitter at the input is known?

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