i am getting noiser output spectrum,i am attaching spectrum analyzer snapshot, i am using 20 MHz TCXO,Sys clk running at 1GHz (Multipliar of 50).Sys clk/4 output is disabled. pl suggest where is the problem.
Are you using the AD9957 evaluation board? Or your own board? If your own board, would it be okay to take a look at the schematic?
As stated in the datasheet, if you are using a crystal as reference clock of AD9957, it is recommended to use 25MHz frequency.
Disabling SYNC_CLK output is okay but it is still advisable to enable it for monitoring purposes.
i am using my own board,i am attaching the schematic of my board in which U29 is the AD9957.R52,R62,R106 is open circuit in ref clk circuit.right now i cant change the TCXO.
Sorry for a very late reply.
I noticed that the Pin 95 (XTAL_SEL) is connected to AGND via a 10k resistor. However, if you are using a TCXO, this pin must be connected to a 1.8V so that you will enable the internal oscillator that goes with a single crystal operation.
Hope this helps.
1. Where is masured attached "AD9957.png" ? There are TP27, TP28, TP29, TP40...
2. Input spectrum needed spectrum analyzer snapshot from U25 / pin3 !
3. C98 will be 10 uF, and C97 will be 0,1 uF. It is very important!
1. IT IS MEASURED AT TRANSFORMER PAD ,THE OUTPUT CIRCUT(MEANS RESISTANCE,TRANSFORMER ARE NOT FITTED IN THE PCB) IS NOT MOUNTED IN PCB.
2. C98,C97 has same value 10 uf &.1 uf but how they will affect the performace.
3. U25 output snapshot is not availble but i seen it has greater than 60 dB SFDR at same spectrum analyzer setting.
- There ceramic 0,1 uF will be placed as close as possible to U25 /pin 4!
- R52; R62; R106 will be installed on PCB for matching & right measurement.
Message was edited by: Georgy Shebetovskiy
Datasheet from U25:
- A 0.01uF and a 0.1uF capacitor should be located as close to the supply (pin 4) as possible (to ground) is recommended.
- A pin 1 should be grounded (but not set to a voltage such as the supply).
So try pin 1 set on ground.
NOTE: Additional pads are used to program and adjust the TCXO during manufacturing and should be left
open; do not terminate these to the supply voltage. Some designs do not include these additional pads.
It’s recommended to not have traces routed underneath the devices.
Per the external loop filter component values, you may have an issue with the internal PLL loop stability. So let's rule that out first. I have attached the online PLL tool's URL for downloading. See if the tool agrees with you values or not. Hope this helps. http://www.analog.com/en/digital-to-analog-converters/direct-digital-synthesis-dds/ad9957/products/EVAL-AD9957/eb.html
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