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AD9781 Bist Feature

Question asked by nikhil on Feb 5, 2013
Latest reply on Feb 6, 2013 by Tguy

Hi,

 

If I am correct then in AD9781 the BIST mechanism samples the digital input data at the rising and falling edge of the CLK (DAC sampling clock) and keeps on adding them with the previously sampled data.

Do we need to optimize the parallel port timing (SEEK and HLD delays) first before using this BIST feature.

 

Thanks and Regards,

Nikhil

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