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AD9726 clocks

Question asked by jharris on Feb 4, 2013
Latest reply on Feb 4, 2013 by larrywelchusa

I am planning on using the AD9726 for a design since it seems to provide the lowest noise performance of an DAC that needs to run at 40MHz (seems like if I need to run at over 10MHz, I need to use a part that is capable of running at a lot more than 40MHz).


I am also planning to use 2 AD9726 in parallel for two data streams that need to have the same delay.  Therefore, I was going to bypass the data sync mode. 


The datasheet has conflicting information, so I wanted to know what to do with the clocks when I use it in this mode:





I know that in this mode CLK+/- is used to clock the data, so do I leave DCLK_IN and OUT unconnected (and do I ground DCLK_IN)?  And then I have a clock chip provide a CLK+/- to the FPGA (feeds AD9726) and AD9726?


Thank you