ADXL346 can work in a trigger mode where once trigger bit D5 of FIFO_CTL register is set either to INT1 or INT2 and bits (D7 D6) of this register are set to trigger mode (1 1) the FIFO will hold the last data samples before trigger event. What I would like to achieve is that when I trigger lets say on INT1 I get a single data point and so on one trigger - one data point. How this mode of operation can be achieved? Can this be achieved by bypassing FIFO all together or by setting FIFO_CTL's D4 D3 D2 D1 bits to hold just one sample in trigger mode? Does anyone of you has experience in working with ADXL345/346 in trigger mode and can share your thoughts on this? Are there any pitfalls in this mode like random time delays between trigger event and data appearing in FIFO? I need this to synchronize ADXL with another piece of hardware so both collect different data on the same trigger edge.