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CPLB Setting

Question asked by mhelmikh on Aug 26, 2009
Latest reply on Aug 27, 2009 by Andreas

I am trying to use DCPLB as it is mentioned in"Watchpoint register operation--Processor hardware challenge" disscussion.

 

I set ENDCPLB bit of DMEM_CONTROL
I put *pDCPLB_DATA0 = PAGE_1K | DCPLB_VALID | DCPLB_SUPV_WR in DCPLB_DATA0
and 0-21 upper bit of Data address

#define PAGE_1K                0x00000
#define DCPLB_VALID        0x1
#define DCPLB_SUPV_WR        0x10

then I access the data so for the first time I have to expect to get an
exception because the cache is empty of that part of memory but I am not
getting Exception!!
Am I missing sth for example do I have to empty Cache in the begining? How
do I have to do that?

Is there any simple code to set DCPLB and ICPLB I would be able to use it?

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