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Question about AD9910 Spur. & some other question about register bit.

Question asked by JongWon on Jan 31, 2013
Latest reply on Jan 31, 2013 by KennyG



I'm using AD9910.


My ref_clk = 40MHz.


PLL use. N : 14.


So, my system clk = 560MHz.


If I make 220 MHz,


Spurs( at 180MHz, 200MHz, 240MHz, 260MHz) present.


Please give me some advice about that.




in CFR3(0x02), What means "REFCLK input divider ResetB" bit?


If I that bit makes 1(normal operation input divider), PLL lock ok, but spurs(every 20MHz) present.


If I that bit makes 0(reset), output does not show.