When I read AD9122's datasheet, I find that register 0x0D[3:2]=11 and 10 are all for 4 ?
On the VCO to DAC frequency we support a ratio of 1,2 or 4 . So the the binary setting of register 0x0D bits 3:2 of both 10 or 11 set a divide ratio of 4. We don't support 8.
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