Should I buffer the LVDS Outputs of the AD9650-105?
We are currently designing two separate boards. The first board will contain the AD9650 and another board will contain the FPGA. The two boards will utilize samtex high speed connectors (QSH) and some type of shielded twisted pair cable assembly to connect both boards. Length from AD9650 LVDS outputs of one board to the FPGA inputs on the other board will be approx 6" to 10" max. The LVDS rate is 160megabits/s. Can I connect the AD9650 LVDS outputs directly to the samtec connector with any repeater/buffer? Also on the FPGA receiving board can I simply connect the LVDS signal directly to the FPGA (with the proper termination)?
I did notice in several Analog Devices demo boards that buffers/repeaters were not used. In one particular ref design of an ADC (AD9467) no buffer/repeaters were utilized to drive the LVDS from the AD9467 through a large interposer board, then to a Xilinx KC705 eval FPGA. The data sheet noted that 18" is OK for the AD9467 LVDS outputs. Does this also apply for the AD9650 LVDS outputs?
Also I was curious if the AD9650 LVDS outputs support short circuit protection?