It seems there are contradiction in ADF4350 datasheet for the fast lock timer configuration. In page 22 of the datasheet, it says
"Note that the duration the PLL remains in wide bandwidth is equal to the fast-lock timer/fPFD."
It also says in the same page that
"Fast-Lock Timer Value = Time in Wide Bandwidth × fPFD/MOD"
The wide bandwidth duration in these two places have a MOD difference. In the ADF4350 evaluation board software, it uses the first equation to calculate the time. Would you pls check which one is correct?