I downloaded the reference design cf_adv7511_zed and built it from the source files. There are no timing errors if I use the IP versions specified in the mhs file. However, some of those versions are out of date. In particular, processing_system_7 is at version 3.00.a. When I update processing_system_7 to the current rev of 4.03.a, the design no longer meets timing. In particular, clk_fpga_1 should be 200MHz, but the routed design can only achieve 154MHz. Has anyone figured out how to update this design and get it to run at speed?