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AD9467_FMC_250_EBZ + VC707 sample rates

Question asked by on Jan 29, 2013
Latest reply on Jan 31, 2013 by



I just started using the AD9467_FMC_250_EBZ board with the VC707. I have followed the instructions at and everything is working as expected, provided I drive my ADC clock at 240-250MHz. The software finds the zero-error delay setting and the data look clean in ChipScope.


Any slower than 240MHz and I get the error:

"adc_setup: can not set a zero error delay!",


and I get corrupted data in ChipScope. Because the instructions say "The clocks must be running on the FMC board before FPGA is programmed.", I am reprogramming the FPGA each time I change frequencies. I was previously running the reference design on the ML605 and I was able to run from 250MHz all the way down to 50MHz.


Does anybody have insight into what might be causing this problem? Thank you!