Hi there,

I need your help about AD9956 register configuratin. I've searched many topics about AD9956 and found many kinds of answers. Take RSRR for example, DSB said that the ramp rate is RSRR/SYNC_CLK in here:http://ez.analog.com/message/18170, but equals RSRR (decimal) / 2^16 * SYNC_CLK in here:http://ez.analog.com/message/23306#23306. Has anyone verified the correct configuration? Another confusion is rising frequency step size, DSB also said here http://ez.analog.com/message/23306#23306. that it equals RDFTW (decimal) / 2^32 * the system clock rate. But I can not find any resgister that is 32 bits long. Does anyone verified this? Is it really 32 bits or 24 bits or 48 bits? Thank you very much.

Hi,

Sorry for the late reply.

Ramp rate:

Ramp rate is dependent on the SYNC_CLK cycles, and SYNC_CLK = SYSCLK/4.

Thus, if you have SYSCLK = 400MHz(maximum for AD9956), your SYNC_CLK will be 100MHz.

The fastest ramp rate you can have is 10ns. That is:

RSRR (decimal) = 1

ramp rate (Δt) = RSRR/SYNC_CLK = 1/100MHz

So for example, given you have SYSCLK = 400MHz and you want a 1us ramp rate (Δt), the value of your RSRR (decimal) = 100.

Frequency Step Size:

step size = [RDFTW (decimal) / 2^24] * SYSCLK

Ex:

the smallest frequency step size you can have in a SYSCLK of 400MHz is:

step size = [1/ (2^24)] * 400M = 24Hz.

Hope this clears your confusion.

Best Regards,

Sitti