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Confusion about AD9956 register configuration.

Question asked by dsx on Jan 28, 2013
Latest reply on Jan 31, 2013 by dsx

Hi there,

 

I need your help about AD9956 register configuratin. I've searched many topics about AD9956 and found many kinds of answers. Take RSRR for example, DSB said that the ramp rate is RSRR/SYNC_CLK in here:http://ez.analog.com/message/18170, but equals RSRR (decimal) / 2^16 * SYNC_CLK in here:http://ez.analog.com/message/23306#23306. Has anyone verified the correct configuration? Another confusion is rising frequency step size, DSB  also said here http://ez.analog.com/message/23306#23306. that it equals RDFTW (decimal) / 2^32 * the system clock rate. But I can not find any resgister that is 32 bits long. Does anyone verified this? Is it really 32 bits or 24 bits or 48 bits? Thank you very much.

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