Is there any integrated solution by ADI that offers voltage translation between 1V8 and 3V3 I2C buses?
The ADuM1250 does the level translation job as a byproduct of the isolation. The minimum supply voltage is 3.0V. This is for two reasons, first to support driving pulses across the barrier, secondly because the VOL on side 1 is up to 0.9V which is not compatible with 1.8V logic. So within the supply range 3-5.5 we can be a level translator, but below that range it becomes more difficult.
However, If you can create a 2.1V, I2C pull-up voltage on the low voltage side, there is a mode that would work because the bus pull-up does not actually need to be pulled to the VDD of our part. Generate a 2.1V rail for the bus, and run VDD2 at 3.0V for the ADuM1250. The 2.1V bus should not be so far above the 1.8V FPGA that it would trigger the ESD protection diodes to conduct, so it should be compatible. Since the logic levels will not be at 50% of VDD any longer, there may be additional pulse width distortion, that may need to be analyzed. It should work, but be careful to do the 1.8V interface on side 2 of the ADum1250, side 1 will be more complicated due to the non standard logic levels.
I just ran across this, and wanted to point out that there might be a related thread regarding the ADG3245. See ADG3245 for SPI and I2C
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