Please let me know if there is a reference document showing which registers of AD9970 have to be programmed and what is the value.
The tons of time caould be saved by this documents.
I am checking with the expert here on this part and hope to have a response soon.
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Just to follow-up on the offline reply, here are some example settings for the AD9970 that you can modify for your system. Also, be sure to refer to the Recommended Power-Up Sequence in the data sheet for specific instructions on power supplies, clocks, and required delays between certain register writes.
I have used the reference code you sent me to update the registers of AD9970.
It is working but with the wrong Horizontal and vertical timing.
I have tried to modified the Horizontal and vertical timing by writing to 0x800 to 0x81f but without any luck.
If it is possible, please give me a simple example of register setting since the explanation inside AD9970 datasheet is not clear and even the 0x810 to 0x81f don’t exist inside manual.
Many thanks for your helps.
For question 1, please take a look at page 42 of the data sheet, "Layout of Internal Registers". Regarding PBLK, this is not a required signal, so you can choose not to use it if you prefer. For question 3, can you please provide more information on what you are trying to achieve- the SYNC sequence is supposed to output all words together at the start of each line, or at the specified trigger locations.
Many thanks for you answers.
Regarding to questios 3, I have solved it.
Before I only used three sync words, FPGA can't detect them all for each line since the nosiy data can corrupt the detection.
I am currently used all seven sync words and FPGA can detect them all.
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